With continuous developments of a process of manufacturing a semiconductor chip, a size of the semiconductor chip has continuously decreased. Currently, since the size of the semiconductor chip is greatly decreased, when forming a semiconductor package, it is necessary to increase a size of the semiconductor package for electrical connection. One of semiconductor package technologies proposed in the process of the developments is a fan-out package. Further, technology expanding a memory capacity or improving operating performance of a semiconductor chip in the same installation dimension by forming a pattern structure transferring a signal in a vertical direction in an outer region of the fan-out package and stacking packages of the same kind or packages of different kinds has also been developed in various types.
A conventional art forms a hole in an outer molding region of the semiconductor chip in order to connect an electrical signal vertically, fills a conductive paste therein, and forms a through pattern having a vertical shape. After this, the conventional art forms a horizontal pattern which is electrically connected to the through pattern and is formed in the upper and/or lower surface of the outer molding region. However, the conventional art generates various process defects due to damage of a surface of a chip pad or penetration of a molding material, etc. during a manufacturing process. Further, the conventional art has limitations that it is difficult to precisely form the through hole for forming the through pattern which is formed in the molding region of the semiconductor chip and densely fill the through hole with a conductive material. There is U.S. Pat. No. 7,545,047 as a prior art document.